SSC IMD SA Mock 02 – Question 108

A 4-way set-associative cache memory has a total size of 64 KB with a cache block size of 64 bytes. If the physical address is 32 bits, how many bits are used for Tag, Set Index, and Block Offset respectively?

• 18 bits, 8 bits, 6 bits
• 16 bits, 10 bits, 6 bits
• 20 bits, 6 bits, 6 bits
• 17 bits, 9 bits, 6 bits

Step-by-step derivation:
1. Block size = 64 bytes = \(2^6\) bytes \(\implies\) Block Offset = 6 bits.
2. Total number of blocks in cache = \(\frac{\text{Cache size}}{\text{Block size}} = \frac{64\text{ KB}}{64\text{ B}} = \frac{2^{16}}{2^6} = 2^{10} = 1024\) blocks.
3. Since it is 4-way set associative, each set contains 4 blocks.
Number of sets = \(\frac{1024}{4} = 256 = 2^8\) sets \(\implies\) Set Index = 8 bits.
4. Tag bits = \(\text{Physical Address bits} – \text{Set Index} – \text{Offset} = 32 – 8 – 6 = 18\) bits.
Therefore: Tag = 18 bits, Set Index = 8 bits, Offset = 6 bits.