DSSSB TGT CS 2023 Shift 2 – Question 128

A _____ counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock input of the following flip-flop.

• ripple
• synchronous
• ring
• cascaded

In digital electronics:
– A **ripple counter** (also known as an **asynchronous counter**) is a cascaded arrangement of flip-flops in which the external clock signal triggers only the first flip-flop, and each subsequent flip-flop is clocked by the output of the preceding flip-flop. The signal ‘ripples’ through the counter stage by stage.
– In a **synchronous counter**, all flip-flops share a common clock pulse and transition simultaneously.
– A **ring counter** is a circular shift register where the output of the last flip-flop is connected back to the first flip-flop.

Thus, the correct term is **ripple** (Hindi: ऊर्मिका).